1. Field of the Invention
The present invention relates in general to data processing systems, and more particularly relates to a floating point unit for making floating point calculations within the data processing system.
2. Description of Prior Art
The representation of numbers in data processing systems, particularly non-integer numbers, requires the introduction of a decimal point into the notation. As one option, data processing systems may employ "fixed point notation" wherein the decimal point is placed immediately to the right of the least significant digit or placed immediately to the right of the signed bit before the first information bit.
A further option is called "floating point notation" in which the number is represented by a sign, an exponent, and a mantissa. Such technique is described in many texts, one example being "Computer Architecture", Caxton C. Foster, Van Nostrand Rheinhold Company, New York, New York, 1976, pp. 16 et seq.
Floating point processing units tend to become relatively complex when designed for use for large decimal ranges and increased precision capabilities. One technique which provides for a relatively good degree of flexibility and good accuracy, using some simplification of conventionally used floating point architecture, is described in Canadian Pat. No. 1,105,065, issued Aug. 2, 1977, to Richard T. McAndrew, and assigned to the assignee of the instant application. Such architecture is designed for shifting first and second operands, such operands having first and second mantissa and exponent values, respectively, for performing arithmetic operations. Arithmetic logic means and register means are provided therein for generating a pre-selected scale factor, to denote operand shifting requirements. Scaler means therein are connected for selectively loading the registers in serial fashion in a first direction and for scaling and operand input in response to the pre-selected scale factor. Switch means are utilized for selectively connecting the register to the scaler means for serially writing out of the selected register in the first direction.
Another technique of the prior art which provides an improvement in speed of operation of mantissa multiplication techniques is provided by performing the operation on four bits of the multiplier mantissa simultaneously as opposed to using single bit mantissa multiplication techniques; this technique is demonstrated in U.S. patent application Ser. No. 871,616, filed Jan. 23, 1978, entitled "Floating Point Data Processing System", inventor, Edward Rasala, and assigned to the assignee of the present application. In this prior art application, the four-bit mantissa multiplication is performed in hexadecimal notation, using appropriately interconnected shifter units, arithmetic logic units, and registers. In accordance with this prior art patent application, the overall operation is effectively a "pipeline" operation wherein a working register always contains a partial product and a final register always contains a partial sum which is fed back into a second arithmetic logic unit to provide a continuous computation. The total product at a final register is supplied to the data processing system by way of an internal mantissa bus to the data bus which provides for data transfer between the processing system and the floating point unit.
While the systems described in the above-referenced prior art patent and patent application have capability for performing rapid and convenient arithmetic operations on a large range of numbers with reasonably high precision and speed, the overall operation of the floating point processor which employs architecture to provide a mantissa calculation function, and exponent/sign calculation function, and a control of both of these other functions, can yet be improved. The present invention provides this improvement in operating speed and efficiency by incorporating techniques which permit simultaneous operation of both the mantissa and exponent functions under a unique control architecture.
Accordingly, the continual challenge or problem of reducing the time for specific calculations and for overall operation of a floating point processor is met by the design or solution of the present invention to be described in detail hereinbelow.